page 1 phone: 360.260.2468 z sales: 800.736.0194 z fax: 360.260.2469 email: sales@usdigital.com z website: www.usdigital.com 11100 ne 34th circle z vancouver, washington 98682 usa LS7183 & ls7184 encoder to counter interface chips the LS7183 and ls7184 allow incremental encoders to drive standard up/down counters. connect the encoder quadrature outputs to the a & b inputs. the LS7183 outputs can connect directly to the up and down clock inputs of counters such as 74193 or 40193. the ls7184 outputs can connect directly to the clock and up/dn inputs of counters such as 4516 or 74169. the LS7183 and ls7184 are improved designs over the ls7083 and ls7084 products and should be considered first for all new product designs. the primary differences between the old and new ls chips are the addition of a x2 resolution multiplication, power supply operating range and improved output pulse timing characteristics. please note: rbias values for output pulse width timing are not the same as the ls7083 and ls7084 values. description: pin 1 (rbias input): input for external component connection. a resistor connected between this input and supply voltage adjusts the output pulse wi dth. see rbias resistor value vs. timing table for further information. pins 4 & 5 (a & b inputs): connect to the a and b quadrature outputs of the encoder. both inputs have debounce filters. minimum pulse width is set at 300n s. there is no maximum limit. input current is less than 1a. the a and b inputs can be swapped to reverse the direction of the external counters. pin 6 (mode input): mode is a 3-state input to select resolution x1, x2 or x4. the input quadrature clock rate is multiplied by factors of 1, 2 or 4 in x1, x2 or x4 modes respectively in producing the output up/dn clocks. x1, x2 or x4 modes are selected by input logic levels as follows: ? mode = 0 vdc = x1 selection ? mode = +vdc = x2 selection ? mode = float = x4 selection in x4 mode, one pulse is generated for each a/b state change. in x1 mode, one pulse is generated per quadrature cycle. in x2, t wo pulses per quadrature cycle. LS7183 pin 7 (down clock output): normally high, low-true. the low level pulse width is set by pin 1. down counts are enabled only when b leads a. ls7184 pin 7 (up/down clock output): this output steers the external counter up or down. high = up (a leads b), low = down (b leads a). LS7183 pin 8 (up clock output): normally high, low-true. the low level pulse width is set by pin 1. up counts are enabled only when a leads b. ls7184 pin 8 (clock output): normally high, low-true. the low level pulse width is set by pin 1. the external counter should count on the rising (high-going ) edge of this output. surface mount package: the 8-pin soic package has the same pin-out as the dip version shown above. pin descriptions: features: ? x4, x2 or x1 resolution multiplication ? ttl and cmos compatible ? low power (micro-amps) ? 8-pin dip or soic package ? no external clocks required ? drive standard up/dn counters ? monolithic cmos ? operates from 3v to 5v power supply parameter min. max. units operating temperature -20 85 c storage temperature -55 150 c voltage @ any input -.3 vcc+.3 volts supply voltage (vcc) 7 volts absolute maximum ratings: 1 2 3 45 6 7 8 gnd a in b in mode input dnclk out upclk out LS7183 1 2 3 45 6 7 8 gnd a in b in up/dn out clock out ls7184 rbias 74193 type cascadable up/dn counte r 5 4 4516 type up/dn counte r 15 10 to p v i e w rbias mode input top view optical encoder optical encoder cascadable float +vdc float +vdc +vdc +vdc
page 2 phone: 360.260.2468 z sales: 800.736.0194 z fax: 360.260.2469 email: sales@usdigital.com z website: www.usdigital.com 11100 ne 34th circle z vancouver, washington 98682 usa LS7183 & ls7184 encoder to counter interface chips parameter min. typ. max. units notes supply voltage 3.0 - - volts supply current - 30 45 ma mode input logic 0 - - 0.6 volts logic 1 vdd-0.6 - - volts logic float (vdd/2)-0.5 - (vdd/2)-0.5 volts a,b inputs logic 0 - - 0.3vdd volts logic 1 0.7vdd - - volts rbias input external resistor 5k - 10m ohm all outputs sink current 1.2 1.8 - ma vout=0.5v source current -1.2 -1.8 - ma vout=2.5v electrical specifications for 3vdc operation: parameter min. typ. max. units notes supply voltage - 5.0 5.5 volts supply current - 110 150 a mode input logic 0 - - 0.6 volts logic 1 vdd-0.6 - - volts logic float (vdd/2)-0.5 - (vdd/2)-0.5 volts a,b inputs logic 0 - - 0.3vdd volts logic 1 0.7vdd - - volts rbias input external resistor 5k - 10m ohm all outputs sink current 2.5 3.5 - ma vout=0.5v source current -2.5 -3.5 - ma vout=4.5v electrical specifications for 5vdc operation: parameter min. typ. max. units notes output pulse width 190 - - ns a,b inputs validation delay - 25 50 ns vdd=5v - 50 100 ns vdd=3v input to output delay - 200 270 ns vdd=3v - 110 150 ns vdd=5v transient characteristics: rbias resistor value vs. timing (typical): resistor pulse max a, b max a, b max a, b width freq. (x1) freq. (x2) freq. (x4) 20kohm 500ns 1000khz 500khz 250khz 220kohm 3.0s 167khz 83khz 42khz 750kohm 9.5s 53khz 26khz 13khz 2.0mohm 28s 18khz 9.0khz 4.5khz 5.1mohm 65s 7.7khz 3.8khz 1.9khz 8.2mohm 119s 4.2khz 2.1khz 1.1khz 10mohm 142s 3.5khz 1.8khz .9khz
page 3 phone: 360.260.2468 z sales: 800.736.0194 z fax: 360.260.2469 email: sales@usdigital.com z website: www.usdigital.com 11100 ne 34th circle z vancouver, washington 98682 usa LS7183 & ls7184 encoder to counter interface chips ordering information: technical data, rev. 06.03.03, june 2003 all information subject to change without notice. dip package (300mil): LS7183-dip or ls7184-dip soic package: LS7183-soic or ls7184-soic price: $3.05 / 1 $2.45 / 25 $1.95 / 100 $1.65 / 500 $1.40 / 1k LS7183 timing diagram: the maximum time delay from the a or b input to the leading edge of any output is 270ns for 3vdc operation and 150ns for 5vdc operation. the pulse width of all clock outputs is set by the value of the rbias resistor as shown in the table above. typical rise or fall time of each logic output 10 to 20ns. timing diagram notes: ls7184 timing diagram: a leads b stopped b leads a upclk dnclk dnclk upclk ch a ch b x4 mode x1 mode x2 mode upclk dnclk ch a ch b ( x1 mode) clock (x4 mode) clock up/dn a leads b stopped b leads a (x2 mode) clock
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